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MRF89XA
3.1
Reset of the Chip
3.1.2
MANUAL RESET
A power-on Reset of the MRF89XA is triggered at
power up. Additionally, a manual reset can be issued
by controlling the TEST8 pin (pin 13).
3.1.1 POWER-ON RESET (POR)
If the application requires the disconnection of V DD
from the MRF89XA, the user should wait for 10 ms
from the end of the POR cycle before commencing
A manual reset of the MRF89XA is possible even for
applications in which V DD cannot be physically
disconnected. The TEST8 pin should be pulled high for
100 μs and then released. The user should then wait 5
ms before using the chip. The pin is driven with an
open-drain output, and therefore, is pulled high while
the device is in POR. Figure 3-3 illustrates the Manual
Reset Timing
communications using SPI. The TEST8 pin should be
left floating during the POR sequence. Figure 3-2
illustrates the POR Timing.
Any CLKOUT-related activity can also be
Note:
used to detect that the chip is ready.
FIGURE 3-2:
POR TIMING DIAGRAM
V DD
Pin 13
Undefined
(output)
Note:
When the TEST8 pin is driven high, an
current consumption of up to 10 mA can
be seen on V DD .
Wait for
10 ms
Chip is ready from this point forward
FIGURE 3-3:
V DD
MANUAL RESET TIMING DIAGRAM
> 100 μs
Wait for
5 ms
Chip is ready from this point forward
Pin 13
(input)
High-Z
1
High-Z
DS70622C-page 56
Preliminary
? 2010–2011 Microchip Technology Inc.
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